High performance, nanowatt power level ADC and FFT based on current sharing neural architecture
Kelowna, British Columbia——January 2026 SiliconIntervention Inc, today announced the successful tape-out of a silicon chip based on IRIS—an advanced signal chain processing technology, designed for direct interfacing to multiple sensor types.
Following the Semiconductor industry Association (SIA) call for action and the subsequent Microelectronics and Advanced Packaging Technologies (MAPT) roadmap commissioned by the National Institute of Standards and Technology (NIST) and developed by the Semiconductor Research Corporation SRC), IRIS is the second example in the roadmap of a high efficiency silicon solution based on architectural innovation, following in the footsteps of a Fractal-D ultra-high efficiency audio IP the company introduced earlier in the year.
The Company worked to tape-out in collaboration with a major international semiconductor company based on specifications required for target applications and future product roadmaps.
“I am very pleased with results of our co-operative work and levels of understanding achieved during this project” commented Allan Cox, SiliconIntervention CEO. “IRIS is a prime example of a neural architecture that can achieve deterministic results while enabling innovative circuit design that meets the MAPT performance targets and we look forward to its adoption in many power and performance critical applications.”
Martin Mallinson, Founder and Chief Scientific Officer commented:
“Based on a neural architecture, IRIS technology represents a genuine breakthrough in analog and mixed signal design methods and circuit design, and is covered by multiple patents.
Efficient operation, based on current re-use technology, enables a complete neural based signal chain to be constructed that includes a Sample and Hold (SHA), Programmable Gain Amplifier (PGA) and Sigma-Delta ADC (SDADC) functionality, interconnected to perform FFT functions.
An example of the efficiency gains can be judged by the performance of the SHA, PGA and SDADC building block which in a 22nm CMOS process typically consumes 760nA (at 1.2v) with a 4kHz Nyquist range.
When interconnected as a neural network, multiple building block instances source neurons with current that enable an FFT function to operate, delivering a new set of analytic FFT results for every clock input sample. The technology roadmap adds a choice of a window function (in the analog domain) such that a 32 bin FFT consumes 1.3uA (at 1.2v) and a 256 bin FFT function consumes 10.4uA (at 1.2v) in the same process.
Martin went on to say “one of the features of the technology is that it only needs “digital “ FET devices and as such matches a wide range of processes, making it readily scalable with voltage and frequency.”
IRIS technology can be mapped to a large variety of commercial CMOS Semiconductor processes, and the advanced operating modes promise to not only efficiently pre-process signal data from sensor signals to digital data but also unburden analysis engines such as MCU, DSP and NN’s.
Future developments include greatly improved sensor functions such as correlation and extending FFT to other mathematical transforms including log and single clock calculation of implicit functions such as square root, divide, square root of sum of squares etc.
Company information—SiliconIntervention is a design and IP licensing company based in Kelowna, BC founded in 2019 it specializes in architectural innovation and mixed signal circuit design.
For more information contact SiliconIntervention at: www.siliconintervention.com